/* * Realtek RTL2831U DVB USB driver * * Copyright (c) 2008 Realtek * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper * Copyright (C) 2009 Antti Palosaari * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * * * Thanks to Realtek for a lot of support we received ! */ #ifndef RTL2831U_H #define RTL2831U_H #define DVB_USB_LOG_PREFIX "rtl2831u" #include "dvb-usb.h" #define deb_info(args...) dprintk(dvb_usb_rtl2831u_debug, 0x01, args) #define deb_rc(args...) dprintk(dvb_usb_rtl2831u_debug, 0x02, args) #define deb_xfer(args...) dprintk(dvb_usb_rtl2831u_debug, 0x04, args) #define deb_reg(args...) dprintk(dvb_usb_rtl2831u_debug, 0x08, args) #define deb_i2c(args...) dprintk(dvb_usb_rtl2831u_debug, 0x10, args) #define deb_fw(args...) dprintk(dvb_usb_rtl2831u_debug, 0x20, args) #define rtl2831u_debug_dump(r, t, v, i, b, l, func) { \ int loop_; \ func("%02x %02x %02x %02x %02x %02x %02x %02x", \ t, r, v & 0xff, v >> 8, i & 0xff, i >> 8, l & 0xff, l >> 8); \ if (t == (USB_TYPE_VENDOR | USB_DIR_OUT)) \ func(" >>> "); \ else \ func(" <<< "); \ for (loop_ = 0; loop_ < l; loop_++) \ func("%02x ", b[loop_]); \ func("\n");\ } #define RTL2831U_USB_TIMEOUT 1000 struct rtl2831u_priv { u8 chip_ver; u8 tuner; }; enum rtl2831u_tuner { TUNER_NONE = 0, TUNER_QT1010, TUNER_MT2060, TUNER_MXL5005S, TUNER_FC2580, }; struct rtl2831u_req { u16 value; /* [2|3] */ u16 index; /* [4|5] */ u16 data_len; /* [6|7] */ u8 *data; }; #define DEMOD 0x0000 #define USB 0x0100 #define SYS 0x0200 #define I2C 0x0300 #define DEMOD_READ DEMOD #define DEMOD_WRITE DEMOD+0x10 #define USB_READ USB #define USB_WRITE USB+0x10 #define SYS_READ SYS #define SYS_WRITE SYS+0x10 #define I2C_READ I2C #define I2C_WRITE I2C+0x10 /*****************************************************************************/ /************ USB register ***************************************************/ /*****************************************************************************/ /* SIE Control Registers ====================================================*/ #define USB_SYSCTL 0x0000 /* USB System Control Register */ #define USB_SYSCTL_0 0x0000 /* USB System Control Register */ #define USB_SYSCTL_1 0x0001 /* USB System Control Register */ #define USB_SYSCTL_2 0x0002 /* USB System Control Register */ #define USB_SYSCTL_3 0x0003 /* USB System Control Register */ /* 0x0004 * Reserved */ #define USB_IRQSTAT 0x0008 /* SIE Interrupt Status */ #define USB_IRQEN 0x000C /* SIE Interrupt Enable */ #define USB_CTRL 0x0010 /* USB Control Register */ #define USB_STAT 0x0014 /* USB Status Register */ #define USB_DEVADDR 0x0018 /* USB Device Address */ #define USB_TEST 0x001C /* USB Test Mode Register */ #define FRAME_NUMBER 0x0020 /* Frame number */ /* 0x0024 * Reserved */ #define USB_FIFO_ADDR 0x0028 /* Address of SIE FIFO RAM */ #define USB_FIFO_CMD 0x002A /* SIE FIFO RAM Access Command */ /* 0x002C * Reserved */ #define USB_FIFO_DATA 0x0030 /* SIE FIFO RAM Data Register */ /* 0x0034 - 0x00F4 * Reserved */ /* Endpoint Registers =======================================================*/ #define EP0_SETUPA 0x00F8 /* Endpoint 0 Setup Packet Lower Byte Register */ #define EP0_SETUPB 0x00FC /* Endpoint 0 Setup Packet Higher Byte Register */ /* 0x0100 * Reserved */ #define USB_EP0_CFG 0x0104 /* Endpoint 0 Configure Register */ #define USB_EP0_CTL 0x0108 /* Endpoint 0 Control Register */ #define USB_EP0_STAT 0x010C /* Endpoint 0 Status Register */ #define USB_EP0_IRQSTAT 0x0110 /* Endpoint 0 Interrupt Status Register */ #define USB_EP0_IRQEN 0x0114 /* Endpoint 0 Interrupt Enable Register */ #define USB_EP0_MAXPKT 0x0118 /* Endpoint 0 Max Packet Size Register */ /* 0x011C * Reserved */ #define USB_EP0_BC 0x0120 /* Endpoint 0 FIFO Byte Counter Register */ /* 0x0124 - 0x0140 * Reserved */ #define USB_EPA_CFG 0x0144 /* Endpoint A Configure Register */ #define USB_EPA_CFG_0 0x0144 /* Endpoint A Configure Register */ #define USB_EPA_CFG_1 0x0145 /* Endpoint A Configure Register */ #define USB_EPA_CFG_2 0x0146 /* Endpoint A Configure Register */ #define USB_EPA_CFG_3 0x0147 /* Endpoint A Configure Register */ #define USB_EPA_CTL 0x0148 /* Endpoint A Control Register */ #define USB_EPA_CTL_0 0x0148 /* Endpoint A Control Register */ #define USB_EPA_CTL_1 0x0149 /* Endpoint A Control Register */ #define USB_EPA_CTL_2 0x014A /* Endpoint A Control Register */ #define USB_EPA_CTL_3 0x014B /* Endpoint A Control Register */ #define USB_EPA_STAT 0x014C /* Endpoint A Status Register */ #define USB_EPA_IRQSTAT 0x0150 /* Endpoint A Interrupt Status Register */ #define USB_EPA_IRQEN 0x0154 /* Endpoint A Interrupt Enable Register */ #define USB_EPA_MAXPKT 0x0158 /* Endpoint A Max Packet Size Register */ #define USB_EPA_MAXPKT_0 0x0158 /* Endpoint A Max Packet Size Register */ #define USB_EPA_MAXPKT_1 0x0159 /* Endpoint A Max Packet Size Register */ #define USB_EPA_MAXPKT_2 0x015A /* Endpoint A Max Packet Size Register */ #define USB_EPA_MAXPKT_3 0x015B /* Endpoint A Max Packet Size Register */ /* 0x015C * Reserved */ #define USB_EPA_FIFO_CFG 0x0160 /* Endpoint A FIFO Configure Register */ #define USB_EPA_FIFO_CFG_0 0x0160 /* Endpoint A FIFO Configure Register */ #define USB_EPA_FIFO_CFG_1 0x0161 /* Endpoint A FIFO Configure Register */ #define USB_EPA_FIFO_CFG_2 0x0162 /* Endpoint A FIFO Configure Register */ #define USB_EPA_FIFO_CFG_3 0x0163 /* Endpoint A FIFO Configure Register */ /* 0x0164 - 0x0F00 * Reserved */ /* Debug Registers ==========================================================*/ #define USB_PHYTSTDIS 0x0F04 /* PHY Test Disable */ #define USB_TOUT_VAL 0x0F08 /* USB Time-Out Time */ #define USB_VDRCTRL 0x0F10 /* UTMI Vendor Signal Control Register */ #define USB_VSTAIN 0x0F14 /* UTMI Vendor Signal Status In Register */ #define USB_VLOADM 0x0F18 /* UTMI Load Vendor Signal Status In Register */ #define USB_VSTAOUT 0x0F1C /* UTMI Vendor Signal Status Out Register */ /* 0x0F20 - 0x0F7F * Reserved */ #define USB_UTMI_TST 0x0F80 /* UTMI Test register */ #define USB_UTMI_STATUS 0x0F84 /* UTMI Status Register */ #define USB_TSTCTL 0x0F88 /* Test Control Register */ #define USB_TSTCTL2 0x0F8C /* Test Control Register 2 */ #define USB_PID_FORCE 0x0F90 /* Force PID */ #define USB_PKTERR_CNT 0x0F94 /* Packet Error Counter */ #define USB_RXERR_CNT 0x0F98 /* RX Error Counter */ #define USB_MEM_BIST 0x0F9C /* MEM BIST Test Register */ #define USB_SLBBIST 0x0FA0 /* Self-Loop-Back BIST register */ #define USB_CNTTEST 0x0FA4 /* Counter Test */ /* 0x0FA8 - 0x0FBF * Reserved */ #define USB_PHYTST 0x0FC0 /* USB PHY Test Register */ /* 0x0FC4 - 0x0FEF * Reserved */ #define USB_DBGIDX 0x0FF0 /* Select Individual Block Debug Signal */ #define USB_DBGMUX 0x0FF4 /* Debug Signal Module Mux Register */ /* 0x0FF8 - 0x0FFF * Reserved */ /*****************************************************************************/ /************ SYS register ***************************************************/ /*****************************************************************************/ /* demod control registers ==================================================*/ #define SYS_0 0x0000 /* include DEMOD_CTL, GPO, GPI, GPOE */ #define DEMOD_CTL 0x0000 /* Control register for DVB-T demodulator */ /* GPIO registers ===========================================================*/ #define GPO 0x0001 /* Output value of general purpose I/O */ #define GPI 0x0002 /* Input value of general purpose I/O */ #define GPOE 0x0003 /* Output enable of general purpose I/O */ #define SYS_1 0x0004 /* include GPD, SYSINTE, SYSINTS, GP_CFG0 */ #define GPD 0x0004 /* Direction control for general purpose I/O */ #define SYSINTE 0x0005 /* System Interrupt Enable Register */ #define SYSINTS 0x0006 /* System Interrupt Status Register */ #define GP_CFG0 0x0007 /* PAD Configuration for GPIO0-GPIO3 */ #define SYS_2 0x0008 /* include GP_CFG1 and 3 reserved bytes */ #define GP_CFG1 0x0008 /* PAD Configuration for GPIO4 */ /* 0x0009 - 0x001F * Reserved */ /* IrDA registers ===========================================================*/ #define IRRC_PSR 0x0020 /* IR protocol selection register */ #define IRRC_PER 0x0024 /* IR protocol extension register */ #define IRRC_SF 0x0028 /* IR sampling frequency */ #define IRRC_DPIR 0x002C /* IR data package interval register */ #define IRRC_CR 0x0030 /* IR control register */ #define IRRC_RP 0x0034 /* IR read port */ #define IRRC_SR 0x0038 /* IR status register */ /* 0x003C - 0x003F * Reserved */ /* I2C master registers =====================================================*/ #define I2CCR 0x0040 /* I2C clock register */ #define I2CMCR 0x0044 /* I2C master control register */ #define I2CMSTR 0x0048 /* I2C master SCL timing register */ #define I2CMSR 0x004C /* I2C master status register */ #define I2CMFR 0x0050 /* I2C master FIFO register */ #endif